The present invention relates to a semiconductor device having a trench MIS (Metal-Insulator-Semiconductor) gate structure and a method for fabricating the same.
A trench gate structure formed by filling a gate electrode in a trench formed in a semiconductor substrate is conventionally applied to semiconductor devices such as an IGBT (Insulated Gate Bipolar Transistor) and a MISFET (Field Effect Transistor), and is advantageous for power supply and the like in particular. For example, an IGBT having a trench gate structure has both a high input impedance characteristic of a MISFET and a low saturated voltage characteristic of a bipolar transistor, and is widely used in an uninterruptible power supply and various types of motor driving devices.
FIG. 10 is a cross-sectional view of a semiconductor device having a conventional trench MIS gate structure disclosed in Japanese Patent No. 2662217. The conventional semiconductor device of FIG. 10 has a flat surface in all masking steps while a vertical contact to a gate electrode can be formed. Specifically, on a multilayered structure of a high concentration drain region 110 and a low concentration drain region 111 of a first conductivity type (N-type), body regions 120a and 120b of a second conductivity type (P-type) spaced from each other by an upward opening trench are formed. The high concentration drain region 110 is connected to a drain contact 117. Also, source regions 121a and 121b of the first conductivity type are formed in portions of the body regions 120a and 120b in the vicinity of the upward opening trench. Metal contacts 118 and 119 for attaining contact with the source regions and the body regions are formed on the source regions 121a and 121b and the body regions 120a and 120b, respectively.
The upward opening trench extends into the low concentration drain region 111 through portions between the source regions 121a and 121b and between the body regions 120a and 120b. A gate insulating film 132 is formed on the inner wall of the upward opening trench, and a gate electrode (vertical gate) 133 is filled in the upward opening trench excluding an upper portion thereof with the gate insulating film 132 sandwiched therebetween. The upper face of the gate electrode 133 is placed at a level within the heights of the source regions 121a and 121b. Also, an insulating film 135 is filled in the upper portion of the upward opening trench on the upper face of the gate electrode 133, and the upper face of the insulating film 135 is planarized to be at the same level as the upper faces of the metal contacts 118 and 119.
Although not shown in the drawing, an insulating film is formed on the structure shown in FIG. 10, so as to give a transistor with a flat face. The semiconductor device (MISFET) having the trench MIS gate structure as described above can be easily fabricated. In addition, vertically extending channel regions 122c1 and 122c2 are formed in portions of the body regions 120a and 120b in the vicinity of the gate insulating film 132 on sides of the trench. The channel region 122c1 is sandwiched between the low concentration drain region 111 disposed below and the source region 121a disposed above. The channel region 122c2 is sandwiched between the low concentration drain region 111 disposed below and the source region 121b disposed above. Since the channel regions 122c1 and 122c2 vertically extend in this manner, carriers are allowed to continuously pass vertically in the downward direction, and therefore, the on resistance can be reduced.